1. Field of the Invention
The present invention relates to a memory device capable of changing data output modes, and more specifically, to a memory device capable of changing data output modes, wherein a flash memory designed in a 16-bit output mode can be tested in an 8-bit output mode.
2. Discussion of Related Art
Generally, a memory device includes a cell array and a redundancy array. If a fail column occurs, it is replaced with a normal column included in the redundancy array.
FIG. 1 is a simplified block diagram of a conventional memory device having a redundancy cell array.
Referring to FIG. 1, the memory device includes a cell array 110, a redundancy array 120, a sense amplifier 130, an address buffer 140, a fail bit detector 150 and an I/O multiplexer 160.
The cell array 110 has a plurality of memory cells. A memory cell connected to a corresponding word line and a bit line is selected according to an input address signal. Cell array 110 is divided into 16 blocks. 16 data bits are output from the cells respectively selected from the 16 blocks according to the address signal. In the case of 32 bits, the cell array 110 could be divided into 32 blocks, where 32 data bits are output. Hereinafter, a case where 16 data bits are output will be described as an example.
The redundancy array 120 includes a plurality of repair cells. The array outputs repair data RDL, which will substitute data bits output from the fail cell included in cell array 110, according to the address signal.
For example, if an address signal is input, 16 data bits (i.e., DL0 to DL15) are output from the cell array 110, and the repair data RDL are output from the redundancy array 120.
The data bits DL0 to DL15, and RDL are input to the I/O multiplexer 160. The I/O multiplexer 160 transfers the data bits DL0 to DL15, and RDL to a pad PAD through I/O lines IO[15:0]. I/O multiplexer 160 also determines which data bits DL0 to DL15 in a received address is in error, according to fail bit signals RIO[3:0] of the fail bit detector 150, and outputs the repair data RDL substituting the data bits that are in error.
Fail bit detector 150 determines whether a fail cell is selected in a corresponding address if address signals A[n:0] are received from the address buffer 140, and then outputs the fail bit signals RIO[3:0], which indicate which data bits DL0 to DL15 are in error, to the I/O multiplexer 160.
More details regarding the operation of the fail bit detector 150 will be described below.
FIG. 2 is a simplified circuit diagram showing the fail bit detector shown in FIG. 1.
Referring to FIG. 2, the fail bit detector includes an address comparator 151 and a fail bit signal generator 152. The address comparator 151 and the fail bit signal generator 152 complement (i.e., match) the number of column bit lines included in the redundancy array 120 of FIG. 1.
Address comparator 151 includes a switch comprising a transistor and a fuse, which are connected serially. The switch may be connected in pairs in a parallel manner to form a pair of a larger switching unit. A plurality of the switching units is connected between a power supply voltage terminal and a ground voltage terminal in a serial manner.
Address comparator 151 will be described in more detail. First switch Ta1 and Fa1 and second switch Tb1 and Fb1 in which a transistor and a fuse are serially connected are connected between a first node N0 (an output node) and a second node N1, thus forming one switching unit. A third switch (not shown) and fourth switch (not shown) in which a transistor and a fuse are serially connected are connected between the second node N1 and a third node (not shown) in a parallel manner, thereby forming a subsequent switching unit. The switches are repeatedly connected in pairs in a parallel manner between the respective nodes. (2n−1)th switch Tan and Fan, and (2n)th switch Tbn and Fbn are connected in a parallel manner between a last (n−1)th node Nn−1 and a (n+1)th node Nn+1, thereby forming the last switching unit. It should be appreciated that the number of switching units provided match the number of bits of an address signal.
Meanwhile, in order for the address comparator 151 to enable signals RENb and REN, a switching element PT1 that operates according to the enable signal RENb can be disposed between the power supply voltage terminal and the first node N0. A switching element NT1 that operates according to the enable signal REN can be disposed between the ground voltage terminal and the (n+1)th node Nn+1.
A plurality of fuses Fa1 to Fan, Fb1 to Fbn included in the address comparator 151 are selectively cut (the cutting state of the fuse is not shown) according to address information on which a fail cell is selected. Accordingly, the address for selecting the fail cell is stored. It should be appreciated that only one of two fuses included in each of the switching units is cut, but two fuses are not cut or connected together at the same time.
Furthermore, the address signals A[n:0] and inverted address signals Ab[n:0] are input to the address comparator 151. The address signals A[n:0] are respectively divided into bits, and are input to gates of transistors Ta1 to Tan included in the first, third, fifth, . . . , (2n−3)th and (2n−1)th switch, respectively. The inverted address signals Ab[n:0]respectively divided into bits, and are input to gates of transistors Tb1 to Tbn included in second, fourth, the sixth, . . . , (2n−2)th and (2n)th switch, respectively.
The address comparator 151 outputs repair enable signals RIOEN and RIOENb if the received address signals A[n:0] coincide with stored addresses. For example, if a fail cell is selected when the address signals A[n:0] are input as ‘11 . . . 110’, only the fuses Fa1, Fb2 to Fbn corresponding to a low bit (i.e., 0) in the address signals are cut in advance. This operation stores a fail address. After the fail address is stored, if the address signals A[n:0] are input as ‘11 . . . 110’, where the fuses Fb1, Fa2 to Fan corresponding to a high bit (i.e., 1) in the address signals are connected, the transistors Tb1, Ta2 to Tan which are serially connected to these fuses Fb1, Fa2 to Fan are all turned on. If such a match occurs (i.e., the address signals match the fail address), the first node N0 (the output terminal) is electrically connected to the ground voltage terminal, and the first and second repair enable signals RIOEN and RIOENb are output as High (i.e., 1) and Low (i.e., 0), respectively, through the first node N0.
When first and second repair enable signals RIOEN and RIOENb are generated, the fail bit signal generator 152 outputs the fail bit signals RIO[3:0] indicating which bits are in error.
Fail bit signal generator 152 includes a switching transistor PT2, which is connected to the power supply voltage terminal and operates according to the second repair enable signal RIOENb, first switch Tc1 and Fc1 connected between a switching transistor P1 (not shown) and a first output terminal, second switch Td1 and Fd1 connected between a ground voltage terminal and the first output terminal, third switch Tc2 and Fc2 connected between the switching transistor P1 and a second output terminal, fourth switch Td2 and Fd2 connected between the ground voltage terminal and the second output terminal, fifth switch Tc3 and Fc3 connected between the switching transistor P1 and a third output terminal, sixth switch Td3 and Fd3 connected between the ground voltage terminal and the third output terminal, seventh switch Tc4 and Fc4 connected between the switching transistor P1 and a fourth output terminal, and eighth switch Td4 and Fd4 connected between the ground voltage terminal and the fourth output terminal.
Four output terminals are implemented corresponding to a case where the output data consists of 16 bits. If the output data were output as 32 bits, another output terminal could be provided, along with two additional switches.
The switches of fail bit signal generator 152 can have a structure in which the transistor and the fuse are serially connected. Further, transistors Tc1 to Tc4, Td1 to Td4 operate according to the first repair enable signal RIOEN.
The plurality of the fuses Fc1 to Fc4, Fd1 to Fd4 included in the fail bit signal generator 152 are selectively cut (the cutting state of the fuse is not shown) depending on which bits corresponding to the fail cell are in error. Accordingly, information on which bit is a ‘fail’ (i.e., in error) is stored.
The fail bit signal generator 152 outputs the fail bit signals RIO[3:0] that inform which bit is in error, when the repair enable signals RIOEN and RIOENb are received. For example, if the first bit is a ‘fail,’ the fuses Fd1, Fc2, Fc3 and Fc4 are cut so that the fail bit signals RIO[3:0] are output as ‘0001’. This operation stores information regarding a fail bit (i.e., the location of a fail bit).
When information on the fail bit is stored, as the repair enable signals RIOEN and RIOENb are input, all the transistors Tc1 to Tc4, Td1 to Td4 are turned on. The power supply voltage or the ground voltage is transferred to the output terminal through fuses that are not cut, and the fail bit signal RIO[3:0] is output as ‘0001’.
The I/O multiplexer 160 of FIG. 1 outputs the repair data RDL originating from the redundancy array 120 to the pad PAD, replacing the data in error according to the fail bit signals RIO[3:0].
FIG. 3 is a simplified circuit diagram showing the I/O multiplexer shown in FIG. 1.
Referring to FIG. 3, 8 selectors 161 to 168 are included in the I/O multiplexer 160. 16 data bits DL0 to DL15 act as inputs to the selectors 161 to 168, respectively, in pairs. In the above example, if the circuit operates in 8-bit output mode, only 8 of the 16 data bits DL0 to DL15 are output from cell array 110. The selectors 161 to 168 operate according to an address signal (for example, referred to as “address bit An”), which is used to select the 8-bit output mode, located within the address signals A[n:0]. In the case of 8-bit output mode, the selectors 161 to 168 use only one of two possible data I/O lines (for example, 100 to 107), respectively.
As such, address bit An of the address signal A[n:0] is used in 8-bit output mode. Thus, fuses such as Fan and Fbn, which correspond to the address bit An, have to be properly cut in the address comparator 151 of FIG. 2.
In 16-bit output mode, since 16 data bits DL0 to DL15 are all used as inputs to the I/O multiplexer, the address bit An is not used to signify 8-bit output mode, and fuses such as Fan and Fbn corresponding to the address bit An are connected (i.e., not cut) so that the address bit An is disregarded. However, if the circuit is designed in 16-bit output mode, and fuses Fan and Fbn are all connected, the circuit cannot operate in 8-bit output mode. Accordingly, tests cannot be performed normally under an 8-bit output mode environment.
As a result, equipment capable of performing tests in a 16-bit output mode has to be additionally provided.